• VDD=VDDQ= 1.5V +/- 0.075V• Fully differential clock inputs operation• Differential Data Strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock• Programmable CAS latency 6, 7, 8, 9, 10 supported• Programmable additive latency 0, CL-1, and CL-2 supported• Programmable CAS Write latency (CWL) = 5, 6, 7• BL switch on the fly• 8banks• Programmable burst length 4/8 with both nibble sequential and interleave mode• Auto Self Refresh supported• JEDEC standard 78ball FBGA(x4/x8)• Driver strength selected by EMRS• Dynamic On Die Termination supported• Asynchronous RESET pin supported• ZQ calibration supported• TDQS (Termination Data Strobe) supported (x8 only)• Write Levelization supported• 8 bit pre-fetch• Average Refresh Cycle (Tcase of 0 °C to 95 °C) - 7.8 µs at 0°C ~ 85 °C - 3.9 µs at 85°C ~ 95 °C• Operating Temperature: 0 to +85 °C• Storage Temperature: -55 to +100 °C• ROHS compliant
